1. Field of the Invention
The present invention relates to a method of fabricating integrated circuits, and more particularly, to a method for monitoring self-aligned contact etching.
2. Description of the Prior Art With the development of the semiconductor process, the width of the metal line can be manufactured in a very narrow range. In an integrated circuit process, a contact hole provides an electrical connect for interconnections with the active region of a semiconductor device. Typically, the contact hole is formed using an etching process. The contact hole is typically generated by etching an insulator layer employing a photoresist as an etching mask. The contact hole provides a portion of active area of semiconductor device for interconnections between semiconductor devices. Referring to FIG. 1, semiconductor devices 4 such as transistor are formed over a semiconductor substrate 2. Sidewall spacers 6 and liner layer 8 are substantially formed on the substrate 2 by using a conventional deposition and etching process. An insulator layer 10 such as oxide is then deposited on the liner layer 8. A photoresist layer 12 is coated on the insulator layer 10 and patterned as an etching mask. Afterward, a self-aligned contact (SAC) etching process is performed with high etching selectivity of spacer or liner (for example S.sub.i N) to insulator layer (for example oxide). The self-aligned contact (SAC) etching process can shrink the contact design rule.
During SAC etching, the reaction gas of carbon-fluorine-contained compounds under plasma generates polymer which can etch oxide layer with high etching selectivity of S.sub.i N film to oxide layer. However, too much polymer deposition may cause oxide layer 10 etching stop while insufficient polymer may result in undesirable etching loss of S.sub.i N spacer or liner layer. Therefore, a method to monitor the SAC etching chamber is important for mass production especially under such high polymer deposition condition. Generally, a wafer with SAC structure is etched and inspected by cross-section SEM for checking S.sub.i N loss and etching stop. However, wafers with SAC structure take a long preparation time and high cost in preparation. Generally, it spends time about three weeks to one month to finish complex steps from forming gate electrode to oxide layer. In addition, a few hundred angstrom SN loss is not easy to characterize. Therefore, a method is needed for accurately monitoring the chamber condition and the corresponding SN selectivity with low running cost.